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| Ordering number: EN 5578 CMOS LSI LC11014-241 Computer Image Signal Processing Full-Color Gray-Scale Processor Overview The LC11014-241 is a pseudo gray-scale processor for TFT-LCD panel displays. It allows TFT-LCD panels with 3, 4, 5 or 6-bit input digital drivers to display the equivalent of 16.7 million colors. It can also be used with XGA panels in 2-pixel parallel input/output mode. Package Dimensions unit: mm 3214-SQFP144 [LC11014-241] Features * Handles 8 bits of input data (256-level gray scale data) for each of the RGB colors * Realizes reduced resolution loss (as compared to dithering techniques) by using intra-frame and inter-frame error diffusion processing * Incorporates a new full-coloration algorithm, formerly best done using computers * Operating mode selection of outputs for 3, 4, 5, or 6-bit drivers * Selectable 2-pixel parallel input/output, serial-input parallel-output, and serial input/output operating modes * 40MHz (parallel input/output), 65 MHz (serial input, parallel output), or 50MHz (serial input/output) maximum clock frequency * Can operate independently of the number of displayed pixels since internal operation is controlled by the horizontal and vertical synchronization signals. * Power-save function to stop the internal operation processing circuits, and output only the clock, sync signals and control signals * Supports 5V input signals at 3.3V supply voltage SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 61297HA (ID) No. 5578--1/13 LC11014-241 Pin Assignment Top view Block Diagram No. 5578--2/13 LC11014-241 Pin Summary I O P NC Input I Output Power No connection O I2 O1 O2 O3 TTL-level input buffer 2mA output buffer 4mA output buffer 4mA 3-state output buffer I1 TTL-level pull-down input buffer No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name VSS IOMD0 IOMD1 TEST0 TEST1 TEST2 TEST3 CLKSEL VDD BD10 BD11 VSS BD12 BD13 BD14 BD15 BD00 VDD VSS BD01 BD02 BD03 BD04 VSS BD05 GD10 GD11 GD12 VDD VSS GD13 GD14 GD15 GD00 GD01 VSS I/O P I2 I2 I1 I1 I1 I1 I1 P O1 O1 P O1 O1 O1 O1 O1 P P O1 O1 O1 O1 P O1 O1 O1 O1 P P O1 O1 O1 O1 O1 P No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name VDD GD02 GD03 GD04 GD05 VSS VDD RD10 RD11 RD12 RD13 VSS VDD RD14 RD15 RD00 RD01 VDD VSS RD02 RD03 RD04 RD05 VDD VSS HSYNC VSYNC HDEN VSS CLK VSS VDD CLKB CTL NC VSS I/O P O1 O1 O1 O1 P P O1 O1 O1 O1 P P O1 O1 O1 O1 P P O1 O1 O1 O1 P P O2 O2 O2 P O3 P P O3 O1 NC P No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name VDD GSPMD0 GSPMD1 GSPMD2 VMD SHDEN SHSYNC SVSYNC SCLK VSS SCTL PWRSV BYPASS SRD07 SRD06 SRD05 SRD04 VDD VSS SRD03 SRD02 SRD01 SRD00 SRD17 SRD16 SRD15 SRD14 VSS SRD13 SRD12 SRD11 SRD10 SGD07 SGD06 SGD05 VSS I/O P I2 I2 I2 I1 I2 I2 I2 I2 P I1 I1 I1 I2 I2 I2 I2 P P I2 I2 I2 I2 I2 I2 I2 I2 P I2 I2 I2 I2 I2 I2 I2 P No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name VDD SGD04 SGD03 SGD02 SGD01 SGD00 SGD17 SGD16 SGD15 VSS SGD14 SGD13 SGD12 SGD11 SGD10 SBD07 SBD06 VDD VSS SBD05 SBD04 SBD03 SBD02 SBD01 SBD00 SBD17 VSS SBD16 SBD15 SBD14 SBD13 SBD12 SBD11 SBD10 DSIFT VDD I/O P I2 I2 I2 I2 I2 I2 I2 I2 P I2 I2 I2 I2 I2 I2 I2 P P I2 I2 I2 I2 I2 I2 I2 P I2 I2 I2 I2 I2 I2 I2 I1 P No. 5578--3/13 LC11014-241 Pin Functions Symbol VDD Pin No. 9, 18, 29, 37, 43, 49, 54, 60, 68, 73, 90, 109, 126, 144 1, 12, 19, 24, 30, 36, 42, 48, 55, 61, 65, 67, 72, 82, 91, 100, 108, 118, 127, 135 I/O - Supply voltage (+3.3V) Function VSS - Ground (0V) Mode selection signals [0 to 2] for the gray-scale mode. The setting process for the mode selection lines is described below. GSPMD0 is the LSB and GSPMD2 is the MSB. Gray-scale mode GSPMD0 GSPMD1 GSPMD2 Intra-frame processing Processing Inter-frame processing Number of valid input bits GSPMD [0:2] 74 to 76 I Number of output bits Gray-scale mode 0 1 2, 6 3, 7 5 Yes 8 3 Yes 8 4 Yes 8 5 Yes 8 6 0 L L L Yes 1 H L L Yes 2 L H L Yes 3 H H L Yes Reserved 4 L L H 5 H L H Yes No 8 4 6 L H H Yes No 8 5 7 H H H Yes No 8 6 LCD module Operating mode for TFT LCD modules with 3-bit source driver Operating mode for TFT LCD modules with 4-bit source driver Operating mode for TFT LCD modules with 5-bit source driver Operating mode for TFT LCD modules with 6-bit source driver Operating mode for TFT LCD modules with 3-bit source driver that perform FRC or other inter-frame processing Do not use gray-scale modes 0 to 3 with TFT LCD modules that perform FRC or other inter-frame processing. Input/output mode select pins. The input/output mode selection lines are described below. IOMD0 is the LSB and IOMD1 is the MSB. Input/output mode IOMD0 IOMD1 Input IOMD [0:1] 2, 3 I Output Input/output mode 0 1 2 VMD SCLK DSIFT 77 81 143 I I I 0 L L Parallel Parallel 1 H L Serial Parallel LCD module XGA-compatible 2-pixel parallel input interface TFT LCD panels 2-pixel parallel input interface TFT LCD panels (serial input is converted to parallel internally) Serial input interface VGA and SVGA TFT LCD panels 2 L H Serial Reserved Serial 3 H H Gray-scale processing algorithm select pin. The LC11011-141 algorithm is selected when high. Normal mode is selected when low or open. Clock signal input. Data is processed according to this clock signal. In input/output mode 1, data is shifted out on both xD0 and xD1 when high. No. 5578--4/13 LC11014-241 Symbol SRD0 [7:0] SRD1 [7:0] SGD0 [7:0] SGD1 [7:0] SBD0 [7:0] SBD1 [7:0] SHSYNC SVSYNC SHDEN Pin No. 86 to 89, 92 to 95 96 to 99, 101 to 104 105 to 107, 110 to 114 115 to 117, 119 to 123 124, 125, 128 to 133 134, 136 to 142 79 80 78 I/O I I I I I I I I I Function Input pins for red, green and blue gray-scale data. SRD07, SRD17, SGD07, SGD17, SBD07, SBD17 are the MSBs. SRD00, SRD10, SGD00, SGD10, SBD00, SBD10 are the LSBs. Input data 00H corresponds to minimum brightness, and FFH to maximum brightness. Note that correct gray-scale display does not occur when an input is set to either the minimum or maximum. If 2-pixel data is set on both SxD0 and SxD1, the display data on SxD0 is displayed first. In input/output modes 1 and 2, inputs SRD1[0:7], SGD1[0:7] and SBD1[0:7] should be tied high or low. Horizontal and vertical synchronization signal inputs. These are the sources for the HSYNC and VSYNC signals. They are also used to control data processing. Active-low signals. Horizontal data valid-period signal input. Set this pin high during periods when the horizontal data is valid. If this signal is not used, tie it high and set the input data to 0 during the horizontal blanking period. LCD control signal input. Input control signal that must be matched to the data signal timing. This is the source for the CTL signal. If the CTL signal is not used, there is no internal signal processing of this input and hence there is no need to input the SCTL signal. CLKSEL is the dot clock output select pin. It is used to select the output mode of the dot clock signal output pin. In input/output modes 0 and 2: When CLKSEL is low, a signal with the opposite phase from SCLK is output from CLK. When CLKSEL is high, a signal with the same phase as SCLK is output from CLKB. In input/output mode 1: When CLKSEL is low, a signal with half the frequency of SCLK is output from CLK. When CLKSEL is high, a signal with the opposite phase from CLK is output from CLKB. Red, green and blue gray-scale data output pins. RD05, RD15, GD05, GD15, BD05, BD15 are the MSBs. RD00, RD10, GD00, GD10, BD00, BD10 are the LSBs. If a 2-pixel data set is on xD0 and xD1, the data on xD0 is displayed first. In input/output modes 1 and 2, outputs RD1[0:5], GD1[0:5] and BD1[0:5] are low. In 3-bit data output mode: RD03, RD13, GD03, GD13, BD03, BD13 are the LSBs. RD0[2:0], RD1[2:0], GD0[2:0], GD1[2:0], BD0[2:0], BD1[2:0] are low. In 4-bit data output mode: RD02, RD12, GD02, GD12, BD02, BD12 are the LSBs. RD0[1:0], RD1[1:0], GD0[1:0], GD1[1:0], BD0[1:0], BD1[1:0] are low. In 3-bit data output mode: RD01, RD11, GD01, GD11, BD01, BD11 are the LSBs. RD0[0], RD1[0], GD0[0], GD1[0], BD0[0], BD1[0] are low. Vertical and horizontal synchronization signal outputs. To match the data signal timing, these outputs are delayed with respect to their input signals. In input/output mode 0, they are delayed by 8 SCLK cycles, and in input/output modes 1 and 2, they are delayed by 16 SCLK cycles. When PWRSV is high, these signals are output without being latched internally. Horizontal data valid-period signal output.To match the data signal timing, this output is delayed with respect to the input signal. In input/output mode 0, they are delayed by 8 SCLK cycles, and in input/output modes 1 and 2, they are delayed by 16 SCLK cycles. When PWRSV is high, this signal is output without being latched internally. LCD control signal output. To match the data signal timing, this output is delayed with respect to the SCTL input signal. In input/output mode 0, they are delayed by 8 SCLK cycles, and in input/output modes 1 and 2, they are delayed by 16 SCLK cycles. When PWRSV is high, this signal is output without being latched internally. Power-save control input. When this input goes high, the internal clock stops and the LSI enters powersave mode. Output data are held high. VSYNC, HSYNC, HDEN and CTL control signals, and either CLK or CLKB are output without being latched internally. Tie low or leave open for normal operation. Gray-scale processing bypass pin. When high, the input signals are latched and output without change. When a high-level input on this pin is sampled on the falling edge of SCLK: in input/output mode 0, output is delayed by 8 SCLK cycles, and in input/output modes 1 and 2, output is delayed by 16 SCLK cycles. Test pins [0:3]; left open for normal operation Must be left open. SCTL 83 I CLKSEL CLK CLKB RD0 [0:5] RD1 [0:5] GD0 [0:5] GD1 [0:5] BD0 [0:5] BD1 [0:5] HSYNC VSYNC 8 66 69 52 to 53, 56 to 59 44 to 47, 50, 51 34, 35, 38 to 41 26 to 28, 31 to 33 17, 20 to 23, 25 10, 11, 13 to 16 62 63 I O O O O O O O O O O HDEN 64 O CTL 70 O PWRSV 84 I BYPASS TEST [0:3] NC 85 4 to 7 71 I I - No. 5578--5/13 LC11014-241 Specifications Absolute Maximum Ratings at VSS = 0V Parameter Maximum supply voltage Input voltage Output voltage Operating temperature Storage temperature Symbol VDD max VIN VO Topr Tstg Conditions Ratings -0.3 to +4.6 -0.3 to +5.8 -0.3 to VDD + 0.3 0 to +70 -40 to +125 Unit V V V C C Allowable Operating Ranges at Ta = 0 to +70C Parameter Supply voltage Input voltage Clock frequency1 Clock frequency1 Clock frequency Symbol VDD VIN fCLK fCLK fCLK Input/output mode 0 Input/output mode 1 Input/output mode 2 Conditions min 3.15 0 - - - typ 3.3 - - - - max 3.45 5.5 40 65 50 Unit V V MHz MHz MHz 1. 1024 768; At timing 60Hz (XGA timing), the display interval is less than 75%. DC Characteristics at Ta = 0 to +70C, VSS = 0V, VDD = 3.15 to 3.45V Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Operating current drain1 Power-save current drain2 Standby current drain3 Symbol VIH VIL VOH VOL ICC ICPS ICST IOH = -2mA IOL = 2mA Conditions min 2.0 - VDD - 0.6 - - - - typ - - - - 110 - - max - 0.5 - 0.4 170 30 100 Unit V V V V mA mA A 1. Input/output mode 0, gray-scale mode 7, fCLK = 32.5MHz, VDD = 3.3V, CL = 15pF, (1024 x 768, measured with 60Hz XGA timing) 2. Input/output mode 0, PWRSV = low, fCLK = 32.5MHz, VDD = 3.3V, CL =15pF (control signals: VSYNC, HSYNC, HDEN, CTL, CLK), all other outputs open 3. VDD = 3.3V, all outputs open, all input pins tied low No. 5578--6/13 LC11014-241 Switching Characteristics at Ta = 0 to +70C, VSS = 0V, VDD = 3.15 to 3.45V, CL = 15pF Parameter SCLK cycle time1 SCLK cycle time2 3 SCLK cycle time4 SCLK high-level pulse width1 SCLK high-level pulse width2 3 SCLK high-level pulse width4 SCLK low-level pulse width1 SCLK low-level pulse width2 3 SCLK low-level pulse width4 HSYNC low-level pulse width HSYNC high-level pulse width CLK propagation delay time1 CLK propagation delay time1 CLKB propagation delay time1 CLKB propagation delay time1 CLK propagation delay time2 3 CLK propagation delay time2 3 CLKB propagation delay time2 3 CLKB propagation delay time2 3 CLK propagation delay time4 CLK propagation delay time4 CLKB propagation delay time4 CLKB propagation delay time4 Data setup time Data hold time Data output propagation delay time1 Data output propagation delay time2 3 Data output propagation delay time2 3 Data output propagation delay time2 3 Data output propagation delay time2 3 Data output propagation delay time4 Control signal setup time Control signal hold time Control signal propagation delay time1 Control signal propagation delay time2 3 4 1. Parallel input, parallel output 2. Serial input, parallel output (1H number of pixels is even) 3. Serial input, parallel output (1H number of pixels is odd) 4. Serial input, serial output Symbol Tsclk Tsclk Tsclk Tschw Tschw Tschw Tsclw Tsclw Tsclw Thpw Tvpw Tpckh Tpckl Tpcbh Tpcbl Tpckh Tpckl Tpcbh Tpcbl Tpckh Tpckl Tpcbh Tpcbl Tdsu Tdhd Tpdata Tpdt0sl Tpdt1sl Tpdt0sh Tpdt1sh Ttdatass Tcsu Tchd Tpctl Tpctlsp min 25 15.4 20 10 6.2 8 10 6.2 8 2Tsclk 2Tsclk 7 7 6 7 7 8 7 8 7 7 6 8 5 5 8Tsclk + 9 16Tsclk + 9 15Tsclk + 9 15Tsclk + 9 16Tsclk + 9 16Tsclk + 9 5 5 8Tsclk + 8 16Tsclk + 8 typ - - - - - - - - - - - 11 11 10 12 12 13 12 13 11 11 10 12 - - 8Tsclk + 14 16Tsclk + 15 15Tsclk + 15 15Tsclk + 15 16Tsclk + 15 16Tsclk + 14 - - 8Tsclk + 13 16Tsclk + 13 max - - - - - - - - - - - 22 22 20 24 24 25 23 26 22 22 20 25 - - 8Tsclk + 28 16Tsclk + 29 15Tsclk + 30 15Tsclk + 29 16Tsclk + 30 16Tsclk + 27 - - 8Tsclk + 24 16Tsclk + 26 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns No. 5578--7/13 LC11014-241 Timing Diagrams Input/output mode 0 (parallel input, serial output) No. 5578--8/13 LC11014-241 Input/output mode 1 (serial input, parallel output: 1H number of pixels is even) No. 5578--9/13 LC11014-241 Input/output mode 1 (serial input, parallel output: 1H number of pixels is odd) No. 5578--10/13 LC11014-241 Input/output mode 2 (serial input, serial output) No. 5578--11/13 LC11014-241 Usage Notes Parallel input, parallel output Serial input, parallel output No. 5578--12/13 LC11014-241 Serial input, serial output Usage Note Since this LSI performs spatial modulation using an error diffusion algorithm, patterns that differ from the original images may be displayed for certain display pattern and gray-scale mode combinations. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees, jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. s s This catalog provides information as of June, 1997. Specifications and information herein are subject to change without notice. No. 5578--13/13 |
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